Real Processing in Phase Change Memory

ERC (European Research Council)HORIZON-ERC-POCID: 101069336
EC Contribution
€1,500
Consortium Size
1 orgs
Start Year
2022
▶Summary

Separation of processing and memory is the root cause of the main performance and energy bottlenecks in modern computers. In the PI's ERC Stg, we proposed to combine data processing and storage in the same cells, to develop a novel unit called the 'memristive memory processing unit' (mMPU). This unit was based on resistive RAM (RRAM), which is still not commercial in large capacity. A different memory technology, phase change memory (PCM), is commercially available in large capacity (for example, Intel's Optane has 1.5 TB memory), and can serve as an appropriate technology to form an mMPU with short time-to-market.In this PoC, we aim to experimentally demonstrate a working mMPU based on commercially-available PCM.This mMPU will enable fast and energy efficient computers that are cheaper than existing computers. This will impact different applications such as artificial intelligence, databases, and genomics. The mMPU-based computers will allow faster and cheaper execution of the aforementioned applications.In this proposal, we target the required technical and business steps required to develop such an mMPU and to commercialize it.

Consortium (1)

🇮🇱 TECHNION - ISRAEL INSTITUTE OF TECHNOLOGYIL
coordinator

Project Results (9)

Source: CORDIS, the EU research results database.

▶Publications (8)
Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory
IEEE interregional NEWCAS Conference· 2023DOI
Ben Perach, Ronny Ronen, Shahar Kvatinsky
AritPIM: High-Throughput In-Memory Arithmetic
IEEE Transactions on Emerging Topics in Computing (TETC)· 2023DOI
Orian Leitersdorf; Dean Leitersdorf; Jonathan Gal; Mor Dahan; Ronny Ronen; Shahar Kvatinsky
Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory
IEEE International System-on-Chip Conference (SOCC)· 2023DOI
Perach, Ben; Ronen, Ronny; Kvatinsky, Shahar
Experimental Demonstration of Non-Stateful In-Memory Logic with 1T1R OxRAM Valence Change Mechanism Memristors
IEEE Transactions on Circuits and Systems II: Express Briefs· 2023DOI
Henriette Padberg, Amir Regev, Giuseppe Piccolboni, Alessandro Bricalli, Gabriel Molas, Jean Francois Nodin, Shahar Kvatinsky
FourierPIM: High-throughput in-memory Fast Fourier Transform and polynomial multiplication
Memories - Materials, Devices, Circuits and Systems· 2023DOI
Orian Leitersdorf, Yahav Boneh, Gonen Gazit, Ronny Ronen, Shahar Kvatinsky
On Consistency for Bulk-Bitwise Processing-in-Memory
2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)· 2023DOI
B. Perach, R. Ronen, and S. Kvatinsky
Performing Stateful Logic Using Spin-Orbit Torque (SOT) MRAM
IEEE International Conference on Nanotechnology (NANO)· 2022DOI
Barak Hoffer, Shahar Kvatinsky
Stateful Logic Using Phase Change Memory
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits· 2022DOI
Hoffer, Barak; Wainstein, Nicolas; Neumann, Christopher M.; Pop, Eric; Yalon, Eilam; Kvatinsky, Shahar; Hoffer, Barak
▶Deliverables (1)
Data Management Plan
Documents, reports