A multiprocessor system on chip with in-memory neural processing unit

Digital, Industry & SpaceHORIZON-RIAID: 101070634
EC Contribution
€79,527
Consortium Size
15 orgs
Start Year
2022
Summary

Deployment of intelligence at the edge presents many challenges because devices need to be low-cost and, as such, they are often constrained in computing capacity, memory, and energy resources.These constraints are not compatible with the need for much more advanced AI algorithms calling for Mbytes of storage and tens of GOPS per inference and call for leaner edge AI algorithms. The current state of the art for (the few) edge-AI chips relies on low-cost process technologies at 90 or 40nm and in some cases up to 16nm, with power efficiency between 1-5 TOPS/w and power densities up to 1 TOPS/mm2.Recently several industrial projects and a few products have started to surface pursing neuromorphic and in memory computing, but none of these efforts have reached a level of maturity compatible with a mass volume production and cost, and, moreover the technology base they rely on is either not scalable to more advanced nodes (flash) or, targeting AI computing algorithms whose practical applications are yet to be fully proven (e.g., spiking). The NeuroSoC approach instead is to rely on a solid, mature, and qualified reliable Phase Change Memory technology to create an industrially proven path to go past the state of the art, as such, the NeuroSoC chip pre-product demonstration of the technology will be the first of his kind worldwide.NeuroSoC’s aim is to develop an advanced Multi-Processor System on Chip prototype in FD-SOI 28nm CMOS technology that tightly integrates an AIMC IMNPU unit, a local digital processing subsystem, and functional safe multiprocessor host subsystems based on an enhanced version of existing RISC-V microprocessor implementation, while covering IMNPU security aspects holistically to tackle the requirements of a wide set of edge-AI applications.The project will leverage STMicroelectronics’s unique high-density embedded PCM cell process technology being the denser and only such technology qualified and mature for embedded use in the industry world

Consortium (15)

Project Results (26)

Source: CORDIS, the EU research results database.

Publications (20)
Heterogeneous neural processing units leveraging analog in-memory computing for edge AI
VSLI 2025· 2025DOI
Irem Boybat
IEEE Design and Test
IEEE Design & est· 2025DOI
Philip Wiese; Gamze İslamoğlu; Moritz Scherer; Luka Macan; Victor Jean-Baptiste Jung; Alessio Burrello; Francesco Conti; Luca Benini
Multi-Mode Borderguard Controllers for Efficient On-Chip Communication in Heterogeneous Digital/Analog Neural Processing Units
2025 Design, Automation & Test in Europe Conference (DATE)· 2025DOI
Hong Pang; Carmine Cappetta; Riccardo Massa; Athanasios Vasilopoulos; Elena Ferro; Gamze Islamoglu
On the sampling sparsity of analog-to-spike conversion based on leaky integrate-and-fire
Neuromorphic Computing and Engineering· 2025DOI
Bernhard A Moser; Michael Lunglmayr
A Precision-Optimized Fixed-Point Near-Memory Digital Processing Unit for Analog In-Memory Computing
2024 IEEE International Symposium· 2024DOI
Ferro, Elena; Vasilopoulos, Athanasios; Lammie, Corey; Gallo, Manuel Le; Benini, Luca; Boybat, Irem; Sebastian, Abu
Deeploy: Enabling Energy-Efficient Deployment of Small Language Models on Heterogeneous Microcontrollers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems· 2024DOI
Moritz Scherer; Luka Macan; Victor J. B. Jung; Philip Wiese; Luca Bompani; Alessio Burrello; Francesco Conti; Luca Benini
Designing Circuits for AiMC Based on Non-Volatile Memories: a Tutorial Brief on Trade-offs and Strategies for ADCs and DACs Co-design
IEEE Transactions on Circuits and Systems· 2024DOI
Vignali, Ricardo; Zurla, R; Pasotti, Marco; Rolandi, P. L; Singh, A.; Le Gallo, Manuel; Sebastian, Abu; Jang, Taekwang; Antolini, Alessio; FRANCHI SCARSELLI, Eleonora; Cabrini, Alessandro
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2–8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing
IEEE Journal of Solid-State Circuits, 59 (1)· 2024DOI
Francesco Conti; Gianna Paulin; Angelo Garofalo; Davide Rossi; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggiman; Hayate Okuhara; Luca Benini
On Leaky-Integrate-and Fire as Spike-Train-Quantization Operator on Dirac-Superimposed Continuous-Time Signals
· 2024DOI
Moser, Bernhard A.; Lunglmayr, Michael
On the Solvability of the {XOR} Problem by Spiking Neural Networks
· 2024DOI
Moser, Bernhard A.; Lunglmayr, Michael
Use of RISC-V to develop multiprocessor host subsystems for accelerated platform with In Memory computing based on NVM memories for AI inference answering functional safety requirements for industrial and automotive applications
· 2024
Giulio Urlini and all partners
xTern: Energy-Efficient Ternary Neural Network Inference on RISC-V-Based Edge Systems
IEEE Application-specific Systems, Architectures and Processors· 2024
Georg Rutishauser, Joan Mihali, Moritz Scherer, Luca Benini
A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks
2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)· 2023DOI
Nadalini, Alessandro; Rutishauser, Georg; Burrello, Alessio; Bruschi, Nazareno; Garofalo, Angelo; Benini, Luca; Conti, Francesco; Rossi, Davide
Exploiting the State Dependency of Conductance Variations in Memristive Devices for Accurate In-Memory Computing
IEEE Transactions on Electron Devices· 2023DOI
Athanasios Vasilopoulos, Julian Buchel, Benedikt Kersting, Corey Lammie, Kevin Brew, Samuel Choi, Timothy Philip, Nicole Saulnier, Vijay Narayanan, Manuel Le Gallo, Abu Sebastian
ITA: An Energy-Efficient Attention and Softmax Accelerator for Quantized Transformers
2023 ACM/IEEE International Symposium on Low Power Electronics and Design· 2023DOI
İslamoğlu, Gamze; Scherer, Moritz; Paulin, Gianna; Fischer, Tim; Jung, Victor J.B.; Garofalo, Angelo; BENINI, LUCA
RedMule: A Mixed-Precision Matrix-Matrix Operation Engine for Flexible and Energy-Efficient On-Chip Linear Algebra and TinyML Training Acceleration
Future Generation Computer Systems· 2023DOI
TORTORELLA, Yvan; Bertaccini, Luca; BENINI, LUCA; ROSSI, Davide; Conti, Francesco
Specialization meets Flexibility: a Heterogeneous Architecture for High-Efficiency, High-flexibility AR/VR Processing
2023 60th ACM/IEEE Design Automation Conference (DAC)· 2023DOI
Prasad, AS; Benini, L; Conti, F
Spiking Neural Networks in the Alexiewicz Topology: A New Perspective on Analysis and Error Bounds
· 2023DOI
Moser, Bernhard A.; Lunglmayr, Michael
TOOL-FLOW FOR PERFORMANCE EVALUATION
· 2023DOI
Theodore Antonakopoulos; Iain Keaney
WIP: Automatic DNN Deployment on Heterogeneous Platforms: the GAP9 Case Study
2023 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)· 2023DOI
Luka Macan; Alessio Burrello; Luca Benini; Francesco Conti
Deliverables (6)