Boosting TalTech Capacity in Reliable and Efficient AI-Chip Design

Widening ParticipationHORIZON-CSAID: 101160182
EC Contribution
€12,346
Consortium Size
5 orgs
Start Year
2024
Summary

Building on TalTechs expertise in the field of computer engineering and its high-level capacity in the domain of diagnostics and testing of nanoelectronic systems, this project aims at establishing in TalTech, with the strong support of the Advanced Partners, the capacity to R&D&I a complete customised AI-chip design flow. The research ambition of the TAICHIP (TalTech AI-chip) action is a leading-edge forward-thinking R&D framework for reliable and resource-efficient custom AI-chips based on open HW architectures (e.g., RISC-V, NVDLA), open EDA (Electronic Design Automation) tools, methodologies and implementation technologies satisfying the requirements of AI applications of tomorrow. TAICHIP project also allows building at TalTech the necessary scientific knowledge, research skills, administrative and management skills, as well as strengthening its advanced training and education capacity. Evenly related to the central goal are the additional measures that focus on building the supporting capacities, as well as dissemination, exploitation and communication, and public policy focused activities.

Consortium (5)

Project Results (20)

Source: CORDIS, the EU research results database.

Publications (14)
AdAM: Adaptive Approximate Multiplier for Fault Tolerance in DNN Accelerators
IEEE Transactions on Device and Materials Reliability· 2025DOI
Mahdi Taheri, Natalia Cherezova, Samira Nazari, Ali Azarpeyvand, Tara Ghasempouri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin
AdAM: Adaptive Approximate Multiplier for Fault Tolerance in DNN Accelerators
IEEE Transactions on Device and Materials Reliability· 2025DOI
Mahdi Taheri, Natalia Cherezova, Samira Nazari, Ali Azarpeyvand, Tara Ghasempouri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin
An Efficient Architecture for Edge AI Federated Learning With Homomorphic Encryption
IEEE Access· 2025DOI
Dadmehr Rahbari, Masoud Daneshtalab, Maksim Jenihhin
AxEnMULT: Design of an Efficient and Reliable Approximate Encoding-Based Multiplier
2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)· 2025DOI
Ahsan Rafiq, Alberto Bosio, Salvatore Pappalardo, Maksim Jenihhin
FORTALESA: Fault-tolerant reconfigurable systolic array for DNN inference
Microprocessors and Microsystems· 2025DOI
Natalia Cherezova, Artur Jutman, Maksim Jenihhin
FORTUNE: A Negative Memory Overhead Hardware-Agnostic Fault TOleRance TechniqUe in DNNs
2024 IEEE 33rd Asian Test Symposium (ATS)· 2025DOI
Samira Nazari, Mahdi Taheri, Ali Azarpeyvand, Mohsen Afsharchi, Tara Ghasempouri, Christian Herglotz, Masoud Daneshtalab, Maksim Jenihhin
GENIE: GENetIc Algorithm-Based REliability Assessment Methodology for Deep Neural Networks
2025 11th International Conference on Computing and Artificial Intelligence (ICCAI)· 2025DOI
Samira Nazari, Mahdi Taheri, Ali Azarpeyvand, Mohsen Afsharchi, Christian Herglotz, Maksim Jenihhin
Reliability-Aware Performance Optimization of DNN HW Accelerators Through Heterogeneous Quantization
2025 IEEE 26th Latin American Test Symposium (LATS)· 2025DOI
Samira Nazari, Mahdi Taheri, Ali Azarpeyvand, Mohsen Afsharchi, Christian Herglotz, Maksim Jenihhin
RL-Agent-based Early-Exit DNN Architecture Search Framework
2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)· 2025DOI
Mahdi Taheri, Parth Patne, Natalia Cherezova, Ali Mahani, Christian Herglotz, Maksim Jenihhin
XMULT: An Energy-Efficient Design of Approximate Multiplier
2025 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)· 2025DOI
Ahsan Rafiq, Maksim Jenihhin
FORTUNE: A Negative Memory Overhead Hardware-Agnostic Fault TOleRance TechniqUe in DNNs
· 2024DOI
Samira Nazari, Mahdi Taheri, Ali Azarpeyvand, Mohsen Afsharchi, Tara Ghasempouri, Christian Herglotz, Masoud Daneshtalab, Maksim Jenihhin
Special Session: In-Field ML-Assisted Intermittent Fault Localization and Management in RISC-V SoCs
2024 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)· 2024DOI
Selg, Hardi; Shibin, Konstantin; Tsertov, Anton; Jenihhin, Maksim; Ellervee, Peeter; Raik, Jaan
Special Session: In-Field ML-Assisted Intermittent Fault Localization and Management in RISC-V SoCs
2024 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)· 2024DOI
Hardi Selg, Konstantin Shibin, Anton Tsertov, Maksim Jenihhin, Peeter Ellervee, Jaan Raik
Adaptive Fault Resilience for Early-Exit DNNs
IEEE Asian Test Symposium (ATS'25) (ATS-25)DOI
Kodamanchili, Rama Mounika; Cherezova; Natalia; Taheri, Mahdi; Jenihhin, Maksim
Deliverables (6)