European pilot line for beyond 2nm leading edge System-on-Chip leadership
Digital, Industry & SpaceHORIZON-JU-RIAID: 101183277
EC Contribution
€4,480,067
Consortium Size
6 orgs
Start Year
2024
▶Summary
NanoIC will provide Europe with a beyond 2nm leading-edge SoC pilot line for advanced logic, memory and interconnect technologies to strengthen European leadership in advanced technologies development for markets like computing, communication, mobility, energy and health. The objective of NanoIC is to deliver a 300mm pilot line to the entire semiconductor ecosystem to address the challenges defined in the CPL-1 call of the European Chips Act. Technology development will go up to TRL 3-6 for (i) logic Nanosheet (NS, N2, A14, A10) and Complementary FET (CFET, A7 and beyond) device architectures and high-NA EUV; (ii) the advanced memory options Spin Orbit Torque (SOT)-MRAM, embedded DRAM and 3D-DRAM; (iii) advanced electrical and optical interconnects like die-to-wafer hybrid bonding, fine-pitch re-distribution layer technology chiplet enablement, laser die-to-wafer integration on 300mm photonic interposers.Sustainability is a focus area aimed at energy efficiency, reduction of greenhouse gas emission and water usage of the baseline flows, supported by automated tool and process data acquisition.PDKs on NanoIC baselines for academia, startups, SME’s and industry will be supported by a design enablement facility and training. These include design pathfinding PDKs for prototyping and DTCO at the device and circuit level, and system exploration PDKs for prototyping system functionality combining NanoIC and foundry technologies.Dissemination, Exploitation and Communication actions will engage all stakeholders in pan-European collaborations expanding the community of interest for these advanced technologies. The NanoIC pilot line will build on the collaboration of imec, CEA-Leti (France), Fraunhofer-Gesellschaft (FhG, Germany), VTT (Finland), CSSNT (Romania) and Tyndall Institute (Ireland), but will offer many opportunities for projects with the wider R&D community.
Consortium (6)
🇧🇪 INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUMBE
coordinator🇫🇷 COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESFR
partner🇩🇪 FRAUNHOFER GESELLSCHAFT ZUR FORDERUNG DER ANGEWANDTEN FORSCHUNG EVDE
partner🇫🇮 TEKNOLOGIAN TUTKIMUSKESKUS VTT OYFI
partner🇷🇴 UNIVERSITATEA NATIONALA DE STIINTASI TEHNOLOGIE POLITEHNICA BUCURESTIRO
partner🇮🇪 UNIVERSITY COLLEGE CORK - NATIONAL UNIVERSITY OF IRELAND, CORKIE
partnerProject Results (60)
Source: CORDIS, the EU research results database.
▶Publications (60)
3.5T CFET Block-Level DTCO for Superior PPA in A7 Node by Split Power, hDR Cells, Optimized Pins and BEOL
Lin, Ji-Yung; Kukner, Halil; Yang, Sheng; Verschueren, Lien; Boemmels, Juergen; Dell'Atti, Francesco; Farokhnejad, Anita; Van de Put, Maarten; Zografos, Odysseas; Horiguchi, Naoto; Garcia Bardon, Marie; Hellings, Geert; Ryckaert, Julien
Carrier Mapping in Sub‐2nm Node Nanosheet Transistors with Scanning Spreading Resistance Microscopy
Andrea Pondini, Pierre Eyben, Lennaert Wouters, Albert Minj, Thomas Hantschel, Philippe Matagne, Jérôme Mitard, Anne Verhulst
First Demonstration of Field Free Switching Perpendicular SOT-MRAM 4kb Array Using Z-Spin
Gama Monteiro Junior, Maxwel; Kumar, Ankit; Kateel, Vaishnavi; Vermeulen, Bob; Coester, Birte; Chatterjee, Jyotirmoy; Talmelli, Giacomo; Palomino, Alvaro; Urrestarazu-Larrañaga, Joseba; Van Beek, Simon; Wostyn, Kurt; Rao, Siddharth; NGUYEN, Van Dai; Kar, Gouri Sankar
First Systematic Characterization of Floating Body Effects in GAA Nanosheet 3D DRAM Access Transistors
Garbin, Daniele; Eneman, Geert; Ritzenthaler, Romain; Rassoul, Nouredine; Eyben, Pierre; Canga, Eren; Matsubayashi, Daisuke; Fantini, Andrea; O'Sullivan, Barry; Labbate, L.A.; Loyo Prado, Jana; Loo, Roger; Devulder, Wouter; Dupuy, Emmanuel; Peissker, Tobias; Pacco, Antoine; RAUT, HEMANT; Milenin, Alexey; Wouters, Lennaert; Vrancken, Evi; Beggiato, Matteo; Rosseel, Erik; Kar, Gouri Sankar; Belmonte, Attilio
Hybrid Channel monolithic-CFET with Si (110) pMOS and (100) nMOS
A. Vandooren, S. Iacovo, V. Brissonneau, T. Chiarella, C. Cullen, D. Casey, G. Rengo, R. Khazaka, P. Eyben, V. S. Kumar Channam, J. Ganguly, K. Stiers, C. Sheng, C. Cavalcante, M. Hosseini, D. Batuk, A. Peng, X. Zhou, R. Sarkar, A. Veloso, A. Mingardi, S. K. Sarkar, R. Kumar Saroj, R. Chukka, V. Georgieva, R. Loo, C. Porret, T. Dursap, A. Akula, S. Choudhury, E. Dupuy, A. Peter, N. Jourdan, K. Vandersmissen, D. Montero, E. Vrancken, F. Sebaai, P. Puttarame Gowda, J.-G. Lai, B. T. Chan, A. Sepulveda Marquez, R. Langer, S. Brems, I. Gyo Koo, E. Altamirano Sanchez, K. Devriendt, J. Mitard, L.P.B. Lima, S. Subramanian, N. Horiguchi, S. Demuynck, S. Biesemans
Junction-engineered Scaled High-performance GAA Nanosheet FETs with Ultra-low Temperature (< 350 °C) SiGe: B Source/Drain
R. Sarkar, D. Casey, A. Dutta, P. Eyben, A. Pondini, H. Mertens, T. Dursap, C. Porret, A. Veloso, J. Ganguly, R. Duflou, C. Cullen, P.A. Rathi, M-S. Kim, R. Khazaka, J. Mitard, L. P. B. Lima, S. Biesemans, N. Horiguchi
Low Temperature Site‐Specific Pulsed Laser Annealing of MoS <sub>2</sub>
Nazar Farid, Aashi Gupta, Pavlina Metaxa, A Arifutzzaman, Hariprasad Kuduvan, Rahil Haria, Michele Conroy, Ian Campbell, Ageeth A Bol, James Connolly, Jun Lin, Ian Povey, Ray Duffy, Gerard M O'Connor
Multi-node scaling potential of monolithic CFET
Yang, Sheng; Verschueren, Lynn; Boemmels, Juergen; Kukner, Halil; Lin, Ji-Yung; Bufler, Fabian; Sankatali, V.; Farokhnejad, Anita; Van de Put, Maarten; Hellings, Geert
Novel Low Temperature SiO2 Formation Process by Oxygen and Hydrogen Radicals for Core and I/O RMG Stacks: Achieving the Ultimate NBTI Reliability with a Charge-Free IL
J. Franco, H. Arimura, J. P. Bastos, V. Afanas’ev, J.-F. de Marneffe, M.-S. Kim, B. Kaczer, N. Horiguchi
Understanding and mitigating oxidation-induced electrical instability in sputtered Sc thin films
Jeonho Kim, Indira Kiladze, Clement Porret, Bert Pollefliet, Johan Swerts
2 μm Pitch Direct Die-to-Wafer Hybrid Bonding Using Surface Protection During Wafer Thinning and Die Singulation
Lin, Ye; Bex, Pieter; Suhard, Samuel; Zhang, Boyao; Ulu Okudur, Fulya; Diaz De Zerio, Amaia; Reddy, Naveen K; Altamirano-Sanchez, Efrain; Li, Yanan; Jourdain, Anne; Beyer, Gerald; Beyne, Eric
3D metrology and inspection to enable the rise of stacked transistors, wafers and chips
J. Bogdanowicz, A.-L. Charley, P. Leray, R. G. Liu
Active Sampling of Electrical Characterization Parameters for Efficient Measurement
Koçak, Hüsnü Murat; Mitard, Jerome; Naskali, Ahmet Teoman; Davis, Jesse
Alternative EUV multilayer mirror mask for reduced mask 3D effects evaluated at NA0.33
Tatiana Kovalevich, Nick Pellens, Guillaume Libeert, Lieve Van Look, Andreas Frommhold, Vicky Philipsen, Tsukasa Abe, Yukihiro Fujimura, Izumi Hotei, Mei Ebisawa, Masataka Yamaji, Shosuke Tomizuka, Shingo Yoshikawa
Atomic Force Microscopy: From research lab to High-Volume Manufacturing
A. Moussa, A.-L. Charley, P. Leray
BEFORCE: An advanced, versatile platform for unravelling and quantifying EUV photoresist chemistry during exposure, processing, and interaction with the environment
Ivan Pollentier, Kevin Dorney, Lorenzo Piatti, Fabian Holzmeier, Hyo Seon Suh
Characterization of FOWLP Process Using Temporary Bonding Materials on Carrier with Very Low Die Shift
Tang, Tiffany; Guerrero, Alice; Cuypers, Dieter H.; Macours, Maarten; VAQUILAR, ALDRIN; Bex, Pieter; Kennes, Koen; Phommahaxay, Alain; Beyer, Gerald; Beyne, Eric
Critical in-line OCD metrology for CFET manufacturing
Hyukyun Kwon, Joey Hung, Adam M. Urbanowicz, Ronen Urenski, Igor Turovets, Avron Ger, Szu-Wei Tseng, Mohamed Saib, Janusz Bogdanowicz, Stephanie Melhem, Daisy Zhou, Yong Kong Siew, Debashish Basu, Anne-Laure Charley, Jason Reifsnider, Naoto Horiguchi, Philippe Leray
Defectivity-aware EUV process window characterization for monolithic complementary FET HAR and 3D patterning
Hongcheon Yang, Min-Soo Kim, Xiuju Zhou, Christophe Beral, Anne-Laure Charley, Balakumar Baskaran, Kaushik Sah, Loemba Bouckou, Luca Barbisan, Ganesha Durbha, Nikil Paithankar, Zhijin Chen, Roel Gronheid
Deposition of spinel IGZO thin films with increased indium contents on textured GZO templates
Evangelos Agiannis, Hendrik F. W. Dekkers, Marta Agati, Annelies Delabie
Depth-of-focus enhancement in high-numerical aperture EUV lithography by source and mask optimization
Guillaume Libeert, Joern-Holger Franke, Sofia Leitao, Natalia Davydova, Praniesh Ayyanar Ramachandran, Susan Sherin Kadeparambil Varghese, Vicky Philipsen
Dielectric Breakdown Analysis on Bottom and Top-Gated IGZO-TFT
Van Beek, Simon; Chasin, Adrian; Subhechha, Subhali; Dekkers, Hendrik; Rassoul, Nouredine; Wan, Yiqun; Tang, Hongwei; Bastos, Joao; Belmonte, Attilio; Kar, Gouri Sankar
Disrupting the DRAM roadmap with capacitor-less IGZO-DRAM technology
Attilio Belmonte; Gouri Sankar Kar
Dry etch challenges for patterning middle-of-line (MOL) dual damascene contact trench and via in monolithic CFET (complementary FET)
T. Sarkar, A. Vandooren, K. Stiers, C. Sheng, V. Vega Gonzalez, H. Jenkins, M. Demand, P. Wang, F. Lazzarino, S. Demuynck, N. Horiguchi, S. Biesemans
e-beam Metrology for High-NA: Revisiting the imec Protocol
Gian Francesco Lorusso, Alain Moussa, Sahel Habashieh, Dieter Van Den Heuvel, Diziana Vangoidsenhoven, Mihir Gupta, Hyo Seon Suh, Ying-Lin Chen, Danilo De Simone, Chris Mack, Wei Sun, Masaki Sugie, Philippe Foubert, Miki Isawa, Anne-Laure Charley
Energy-efficient EUV lithography using PFAS-free, light-curable underlayers for advanced nodes
Seonggil Heo, Jelle Vandereyken, Min Seong Jeong, Elke Caron, Wesley Zanders, Seungjoo Baek, Andreia Santos, Douglas J. Guerrero, Veerle Van Driessche, Masahiko Harumoto
Energy-efficient optical crosslinking system and PFAS-free underlayers in ArFi lithography: key enablers for sustainable semiconductor technologies and systems
Min Seong Jeong, Seonggil Heo, Jelle Vandereyken, Elke Caron, Wesley Zanders, Seungjoo Baek, Andreia Santos, Douglas J. Guerrero, and Masahiko Harumoto
Extending the Gate-All-Around (GAA) Era to the A10 Node: Outer Wall Forksheet Enabling Full Channel Strain and Superior Gate Control
Lynn Verschueren; Geert Eneman; Sheng Yang; Jürgen Bömmels; Philippe Matagne; Katty Beltrán Cahueñas, Arvind Sharma, Dawit Abdi, Hans Mertens, Gioele Mirabelli, Geert Hellings
Fundamental Understanding of Exposure and Process Chemistry for Enhanced Lithography and Stability of Metal Oxide Resists
Dorney, Kevin M.; Pollentier, Ivan; Holzmeier, Fabian; Fallica, Roberto; Chen, Ying-Lin; Piatti, Lorenzo; Singh, Dhirendra; Galleni, Laura; Van Setten, Michiel J.; Suh, Hyo Seon; De Simone, Danilo; Pourtois, Geoffrey; Van der Heide, Paul; Petersen, John
Half-Height Double-Row CFET Standard Cells for Area Optimized Placement in A7 CMOS Node
Kukner, Halil; Lin, Ji-Yung; Yang, Sheng; Verschueren, Lynn; Boemmels, Juergen; Farokhnejad, Anita; Van de Put, Maarten; Zografos, Odysseas; Horiguchi, Naoto; Hellings, Geert; Garcia Bardon, Marie; Ryckaert, Julien
Hexagonal Contact Holes patterning at 32 nm pitch: influence of the stack and of the etching process on AEI performances
S. Paolillo, D. Van Den Heuvel, P. Bezard, C. Beral, B. Chowrira, A. Demaude, R. Vallat, L. Souriau, A. Moussa, M. Beggiato, P. Foubert
High NA EUV defectivity inspection: overview and challenges
C. Beral, D. Van Den Heuvel, M. Beggiato, B. Chowrira, S. Paolillo, A. Moussa, P. Foubert, D. Cerbu, A. Demaude, P. Leray, A. L. Charley
IEEE Electron Device Letters
Izukashi, K.; Matsubayashi, Daisuke; Belmonte, Attilio; Kundu, Shreya; Wan, Yiqun; García-Redondo, Fernando; Oh, Hyungrock; Sharma, Arvind Kumar; Subhechha, Subhali; Puliyalil, Harinarayanan; Chasin, Adrian; Dekkers, Hendrik; Pavel, Alexandru; Rassoul, Nouredine; Kar, Gouri Sankar
IEEE Electron Device Letters
Tang, HW; Lin, D; Subhechha, S; Chasin, A; Matsubayashi, D; van Setten, M; Wan, YQ; Dekkers, H; Li, J; Subramanian, S; Chen, Z; Rassoul, N; Jiang, YC; Van Houdt, J; Afanas'ev, V; Kar, GS; Belmonte, A
IGZO Based eDRAM: Bitcell and Array Optimization Enabling Denser Last Level Caches
Sharma, Arvind Kumar; Oh, Hyungrock; Verschueren, Lynn; Subhechha, Subhali; rassoul, Nouredine; Garcia Bardon, Marie; Belmonte, Attilio; Kar, Gouri Sankar; Hellings, Geert; Biswas, Dwaipayan; Garcia Redondo, Fernando
Impact of Mechanical Stress on IGZO TFTs: Enhancing PBTI Degradation
Vishwakarma, Kavita; Lee, Kookjin; Kruv, Anastasiia; Chasin, Adrian; van Setten, Michiel J.; Pashartis, Christopher; Orkut Okudur, Oguzhan; Gonzalez, Mario; Rassoul, Nouredine; Belmonte, Attilio; Kaczer, Ben
Impact of MOR anomalies on lithography and OPC: challenges and solutions
Pervaiz Kareem, Werner Gillijns, Kevin Dorney
In-Poor IGZO: Superior Resilience to Hydrogen in Forming Gas Anneal and PBTI
Kruv, Anastasiia; van Setten, Michiel J.; Chasin, Adrian; Matsubayashi, Daisuke; Dekkers, Hendrik; Pavel, Alexandru; Wan, Yiqun; Trivedi, Kruti; Rassoul, Nouredine; Li, Jie; Jiang, Yuchao; Subhechha, Subhali; Pourtois, Geoffrey; Belmonte, Attilio; Sankar Kar, Gouri
Inline X-ray metrology for Complementary Field-Effect Transistors (CFET)
J. Bogdanowicz, A. Mingardi, V. Brissonneau, R. Loo, Y. Shimura, A. Akula, P. P. Gowda, D. Zhou, N. Horiguchi, S. Biesemans, M. Kuhn, S. Murakami, Y. Ito, A. Higuchi, P. Leray, A.-L. Charley
Journal of Materials Science: Materials in Electronics
Dekkers, Hendrik; Dialameh, Masoud; Agati, Marta; van Setten, Michiel J.; Belmonte, Attilio
mCFET inner spacer cavity etch: process development and challenges
Pallavi Puttarame Gowda, Steven Demuynck, Mohamed Saib, Ann Feyen, Ali Abdelgawad, Naveen Reddy, Alina Arslanova, Alexis Franquet, Rita Tilmann, XiuMei Xu, Beatriz Escorcia Ramirez, Camila Toledo de Carvalho Cavalcante, Andy Peng, Dmitry Batuk, Reda Boufa
Moore's Law meets High-NA EUV: Random via patterning for next-generation nodes
B. Chowrira, V. M. Blanco Carballo, M. Dusa, L. E. Tan, H. Vats, W. Gillijns, S. Decoster, A. Niroomand, V. D. Rutigliani, S. Halder, M. Sangghaleh, D. Tyagi, A. Kamali, M. Newman, M. Demand, Y. Wako, A. Negreira, R. Clark, K. Nafus, M. O'Toole, J. Hsia
Novel concept-oriented synthetic data approach for training generative AI-Driven crystal grain analysis using diffusion model
A.S. Saleh, K. Croes, H. Ceric, I. De Wolf, H. Zahedmanesh
Optimization toward Non-Zero Offset Stability in Overlay Control: Trends and Prospects
Nadav Gutman, Bart Baudemprez, Hongcheon Yang, Christophe Beral, Anne-Laure Charley, Loemba Bouckou, Roel Gronheid, Yaniv Weiss, Sofia Napso, Linoy Nagar-shaul, Chufan Zhang, Dana Klein, Yuval Lamhot, Yuval Lubashevsky, Renan Milo, Efi Megged
Patterning optimization for single exposure BLP and SNLP DRAM layers with 0.33NA and 0.55NA EUV lithography
Van Tuong Pham, Victor Blanco, Jeonghoon Lee, Werner Gillijns, Soobin Hwang, Ardavan Niroomand, Sara Paolillo, Annaelle Demaude, Won Chan Lee, Yannick Feurprier, Kathleen Nafus, Nobuyuki Fukui, Nayoung Bae, Yuhei Kuwahara, Peter De Schepper, Dhruv Tyagi,
Performance Improvement in Sub-2nm Node Nanosheet-FETs Through Optimization of Spacer Interface and Dopant Activation
Pondini, Andrea; Eyben, Pierre; Arimura, Hiroaki; Matagne, Philippe; Chiarella, Thomas; Ganguly, Jishnu; Porret, Clement; Rosseel, Erik; Mertens, Hans; Mitard, Jerome; Verhulst, Anne
Resolution improvement and dose reduction in logic and memory applications from low NA to high NA
Shubhankar Das, Victor Blanco, Van Tuong Pham, Shruti Jambaldinni, Anuja De Silva, Joern-Holger Franke, Marcus Newman, Ali Haider, Matt Gallagher, Jeonghoon Lee, Kaushik Sah, Zhijin Chen, Bobo Cheng, Chenwei Gong, Vidya Ramanathan, Andrew Cross, Werner Gi
Shifter Materials and Stack Explorations for $V_{t}$ Fine-Tunable Dual Dipole Multi-$V_{t}$ Gate Stacks Compatible with Low Thermal Budget CFET
Arimura, Hiroaki; Lukose, Leo; Ganguly, Jishnu; Franco, Jacopo; Mertens, Hans; Stiers, Jimmy; Lai, J. G.; Nalin Mehta, Ankit; Bejide, M.; Kim, Min-Soo; Horiguchi, Naoto
Smart Diagnostics for 3D CFET: A Machine Learning Approach to Failure Analysis
Mitard, Jerome; Koçak, Hüsnü Murat; Chiarella, Thomas; Sheng, Cassie (Jiazhen); Demuyck, Steven; Horiguchi, Naoto
SOT-MRAM Bitcell Scaling With BEOL Read Selectors: A DTCO Study
Xiang, Yang; Garcia Redondo, Fernando; Sharma, Arvind Kumar; Nguyen, Van Dai; Fantini, Andrea; Matagne, Philippe; Rao, Siddharth; Subbhechha, Subhali; Verschueren, Lynn; Baig, Mohammed Aftab; Garcia Bardon, Marie; Hellings, Geert
Stitching at high-NA EUV: a first experimental study
Vincent Wiaux, Natalia Davydova, Nick Pellens, Ataklti Weldeslassie, Jad Haddad, Tatiana Kovalevich, Vito Daniele Rutigliani, Marcus Newman, Mahtab Sangghaleh, Dhruv Tyagi, Airat Galiullin, Jeremy Chen, Adam Lyons, Frank Timmermans, Cyrus Tabery
Stochastic-Aware Compact OPC Model Validation for Reducing Failure Probability
Proc. SPIE 13655, Photomask Japan 2025: XXXI Symposium on Photomask and Next-Generation Lithography Mask Technology· 2025DOI
Renyang Meng, Xuelong Shi, Joost Bekaert, Werner Gillijns, Ryoung-han Kim
Subthreshold swing behavior in amorphous indium-gallium-zinc-oxide transistors from room to cryogenic temperatures
Tang, Hongwei; Belmonte, Attilio; Lin, Dennis; Zhao, Ying(Candice); Beckers, Arnout; Verdonck, Patrick; Dekkers, Hendrik; Subhechha, Subhali; van Setten, Michiel J.; Chen, Zhuo; Kar, Gouri Sankar; Van Houdt, Jan; Afanasiev, Valeri
Thermal conductivity of underlayers for EUV lithography and its effect on sensitivity of metal oxide resist
Roberto Fallica, Danilo De Simone, Patrick E. Hopkins, Andrew Jones, John Gaskins
Tuning, modelling, and verifying effects of intermixing on EUV multilayer mirror performance via a combined simulation and experimental approach
Kevin M. Dorney, Eva Nerke, Katrina Rook, Antonio Checco, Vitaly Krasnov, Ankit Nalin Mehta, Andrea Impagnatiello, Ulrich Klostermann, Andy Dawes, Ulrich Welling, Wolfgang Hoppe, Meng Lee, Vicky Philipsen
Understanding the impact of the EUV photon absorption distribution in a patterned EUV resist and its lithographic performance
Danilo De Simone, Vicky Philipsen, Alessandro Vaglio Pret, Anatoly Burov
Unraveling the role of environment on the lithographic performance of metal oxide resists: key role of oxygen during post-exposure bake
Ivan Pollentier, Fabian Holzmeier, Hyo Seon Suh, Kevin Dorney
Using Programmed defect vehicle to understand printability of defect/2D structures and characterize it through EUV process impact
Bojja Aditya Reddy, Balakumar Baskaran, Mohamed Saib, Joern-Holger Franke, Christophe Beral, Murat Pak, Sandip Halder, Mircea Dusa
Via to line-end contact failures: the role of stochastics
Balakumar Baskaran, Dorin Cerbu, Matteo Beggiato, Victor Blanco, Gian Lorusso, Danilo De Simone, Michael E. Adel, Chris A. Mack
Europes pilot line to enable future compute systems
Nature reviews electrical engineering· 2024
Srikanth B. Samavedam & Jo De Boeck